CMOS S/H circuits are discussed emphasizing speed and linearity. Error sources as well as compensation techniques are examined for charge injection, input dependent sampling time and component nonlinearities. Sampling circuits that do not reset the hold capacitor to an auxiliary condition of zero initial voltage were found to be nonlinear. Sampling circuits in CMOS and bipolar technologies are compared. Charge pump overdrive and type were investigated finding that linearity is a strong function of the sampling time constant. Charge pump driven transmission gate input switches, compensating for gate-source and threshold voltage input dependence, were found to be necessary to maximize the sampling network linearity. Optimal second order OTA (Operational Transconductance Amplifier) settling to a step input was analyzed finding that phase margin is more important than unity gain frequency within a factor of two increase in the unity gain frequency. A prototype circuit with a supply voltage of 5V and a sampling rate of 100 MSPS, consuming approximately 20 mA of current in a 0.5um n-well CMOS process was designed using the flip-around architecture with pumped transmission gates as input switches and a triple cascode OTA with continuous time common mode feedback achieving a simulated SFDR of 98.8 dBc at the Nyquist frequency.